#

migen

Here are 23 public repositories matching this topic...

rprinz08 / hBPF

hBPF = eBPF in hardware

fpga python3 ebpf litex migen

Updated Jan 27, 2023
Python

enjoy-digital / usb3_pipe

USB3 SuperSpeed (5Gbps) and SuperSpeedPlus (10Gbps) for FPGAs without external chip: PHY + Device Core in LiteX.

fpga usb pipe xilinx transceiver mass-storage uvc usb3 litex migen artix7 phy kintex7 cdc-acm gateware ultrascale-plus superspeed superspeedplus

Updated Nov 6, 2026
Python

fomu-workshop

im-tomu / fomu-workshop

Support files for participating in a Fomu workshop

fpga vhdl chisel riscv verilog hdl litex migen fomu fomu-workshop

Updated Mar 17, 2024
Verilog

quartiq / bscan_spi_bitstreams

FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.

fpga migen

Updated Mar 16, 2023
Python

peteut / migen-axi

AXI support for Migen/MiSoC

hdl misoc migen zynq-7000

Updated Oct 1, 2026
Python

fallen / SucreLA

Open source Logic Analyzer based on LiteX SoC

fpga logic analyzer risc-v litex migen ecp5 hydrausb3

Updated Apr 12, 2025
C

sergachev / litex-template

Template project for LiteX-based SoCs

system-on-chip litex migen

Updated May 20, 2026
Python

apertus-open-source-cinema / axiom-micro-gateware

gateware for the main fpga, including a hispi decoder and image processing

fpga image-processing image-sensor axiom migen apertus hispi

Updated Sep 27, 2018
Verilog

JC-LL / ruby_rtl

Describing RTL circuit in Ruby

dsl vhdl hdl digital-circuits migen

Updated Mar 17, 2022
Ruby

zignig / tinybx_stuff

Scripts and gateware for the TinyFPGA bx

migen tinyfpga nmigen

Updated Mar 18, 2020
AGS Script

quartiq / urukul

CPLD gateware for the Sinara Urukul module

fpga cpld artiq migen sinara-hw

Updated Nov 18, 2021
Python

siegeld / ledwall

Drive LED matrix video walls from $15 Colorlight receiver cards — ECP5 gateware, no_std Rust firmware, and a content server. HUB75 and S-PWM panels, streamed video or on-panel programs.

Updated Oct 26, 2026
Rust

quartiq / fastino

Gateware and software for Fastino (32 channel 2.5 MS/s 16 bit DAC for the Sinara ecosystem)

fpga dsp artiq migen sinara-hw

Updated Mar 2, 2023
Python

freddy- / migen-playground

fpga litex migen

Updated Apr 11, 2020
Python

timvideos / qemu-litex

fpga qemu fpga-soc-linux or1k fpga-soc openrisc litex misoc migen liteeth

Updated Sep 13, 2018
C

Bucknalla / warc_fusesoc

WARC Open Fusesoc Cores Repository

hls ip verilog migen open-cores

Updated Mar 17, 2020
Tcl

chmousset / hmmc

Hardware Motion and Motor Control Library

fpga cnc-controller bldc pmsm litex motion-control migen foc motor-control servomotor-control

Updated Jul 22, 2023
Python

MaxenceCaronLasne / unitbench

A unit-test framework for testing Migen modules directely on hardware.

fpga hardware test-framework migen

Updated Jan 23, 2020
Python

anuejn / migen

A Python toolbox for building complex digital hardware [fork for adding nexsys3 support]

fpga metaprogramming migen

Updated May 31, 2017
Python

quartiq / mirny

CPLD gateware for the Sinara Mirny module.

fpga cpld artiq migen sinara-hw

Updated Aug 20, 2024
Python

Add this topic to your repo

To associate your repository with the migen topic, visit your repo's landing page and select "manage topics."