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SPI NOR of Macronix: not taken for SPI NAND, and it erases and writes - #57

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nor-not-nand
Nov 4, 2026
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nor-not-nand

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Macronix SPI NOR chips with the ID c2 20 xx (MX25L4005A up to MX25L51245G, 8 chips of the table) could not be used since 1.10.0.

Detection. The SPI NAND entry MX35LF2G14AC compares only c2 20, and SPI NAND is tried first, so these chips were a 256 MB SPI NAND, and an erase or a write would have gone out as SPI NAND commands. Now an ID of the NOR table wins over a 2-byte SPI NAND entry, and a chip whose registers A0, B0 and C0 all read 0xff is not a SPI NAND, whatever its ID. Both come before any write to the chip. It is the only overlap between the two tables, checked for all three ways of reading the ID.

Protection. Past the detection, -u, erases and writes failed with status register 3 stays 0x07: on Macronix chips 0x35 and 0x15 read something else, and bit 2 of the MX25L12805D's 0x07 was taken for WPS. Only status register 1 counts on them now, and BP3 (bit 5) is cleared with the other BP bits. The reads themselves stay in the output.

Version 1.21.1.

Tests: nandsim covers the 8 IDs, nothing written to the chip, MX35LF2G14AC still found with its own third byte, the 0xff rule; norsim gives Macronix the answers of a real chip (ff, 07).

Hardware: two MX25L12805D, on CH341A and CH347T. Release 1.21.0: both a SPI NAND of 256 MB. This branch: MX25L12805D, 16 MB, -u OK (SR1 0x80 to 0x00 on the one with SRP0), -t OK on both, full dumps before and after identical. A real MX35LF2G14AC is not at hand: only the simulator covers it.

MX25L chips with the ID c2 20 xx matched the 2-byte SPI NAND entry
MX35LF2G14AC, tried first, so they were a 256 MB SPI NAND. An ID of the NOR
table now wins over a 2-byte entry, and a chip whose feature registers all
read 0xff is not a SPI NAND; both before any write to the chip.

Past that, -u, erases and writes failed: 0x35 and 0x15 read something else on
Macronix chips, and the 0x07 of the MX25L12805D was taken for WPS. Only status
register 1 is theirs now, with BP3 in bit 5.

Version 1.21.1.
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PR Summary by Qodo

Fix Macronix SPI NOR detection and write protection

🐞 Bug fix 🧪 Tests 📝 Documentation 🕐 20-40 Minutes

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AI Description

• Prevent overlapping Macronix IDs from selecting SPI NAND commands before any chip writes.
• Clear Macronix BP3 and avoid misinterpreting its other register reads as protection.
• Add simulator coverage and document the fixes in version 1.21.1.
Diagram

graph TD
  Probe["Flash probe"] --> Overlap{"NOR ID overlap?"} -->|Yes| Nor["NOR driver"] --> Protection["SR1 protection"] --> Operations["Erase or write"]
  Overlap -->|No| Features{"All features FF?"} -->|No| Nand["NAND driver"]
  Features -->|Yes| Nor
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High-Level Assessment

The following are alternative approaches to this PR:

1. Probe NOR before NAND
  • ➕ Would resolve known full-ID overlaps without checking them inside the NAND probe.
  • ➖ Changes probe precedence for every chip and does not provide the all-0xff feature safeguard.

Recommendation: Keep the targeted, read-only NAND rejection: it resolves the known overlap before chip writes while preserving probe precedence for other devices. Reviewers should verify that the all-0xff rule is valid for supported NAND chips.

Files changed (6) +107 / -10

Bug fix (2) +55 / -4
spi_nand_flash.cReject SPI NOR matches before NAND initialization writes +43/-0

Reject SPI NOR matches before NAND initialization writes

• Checks the full NOR ID when a NAND entry matches only two bytes, then rejects chips whose three feature registers all read 0xff. The checks run after ID matching but before NAND initialization can write to the chip.

src/spi_nand_flash.c

spi_nor_flash.cCorrect Macronix NOR protection handling +12/-4

Correct Macronix NOR protection handling

• Includes BP3 in the status-register-1 bits cleared for Macronix chips. Unprotect no longer treats reads at 0x35 and 0x15 as status registers 2 and 3 for those chips; QE handling reuses the Macronix identification helper.

src/spi_nor_flash.c

Tests (2) +40 / -5
nandsim.cTest overlapping IDs and read-only NAND rejection +32/-2

Test overlapping IDs and read-only NAND rejection

• Simulates the eight overlapping Macronix NOR IDs and all-0xff feature reads, checking that rejected chips receive no feature-register writes. Also verifies detection of MX35LF2G14AC with its own third ID byte and retention when a feature register responds.

tests/nandsim.c

norsim.cSimulate Macronix register responses and BP3 clearing +8/-3

Simulate Macronix register responses and BP3 clearing

• Models the Macronix reads of 0xff and 0x07 at the status-register-2 and -3 opcodes. Tests BP3 clearing and confirms that ordinary unprotect preserves QE without treating 0x07 as WPS.

tests/norsim.c

Documentation (1) +11 / -0
CHANGELOG.mdDocument the Macronix fixes in 1.21.1 +11/-0

Document the Macronix fixes in 1.21.1

• Adds release notes explaining the NOR/NAND ID collision, the pre-write detection safeguards, and corrected Macronix protection handling.

CHANGELOG.md

Other (1) +1 / -1
main.cSet the application version to 1.21.1 +1/-1

Set the application version to 1.21.1

• Updates the version reported by the application.

src/main.c

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Code Review by Qodo

🐞 Bugs (0) 📘 Rule violations (0) 📎 Requirement gaps (0)

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Great, no issues found!

Qodo reviewed your code and found no material issues that require review

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@compot-dev
compot-dev merged commit ff4fef3 into main Nov 4, 2026
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@compot-dev
compot-dev deleted the nor-not-nand branch November 4, 2026 12:17
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