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SPI NOR: the bits of SR3_DRV0 and SR3_DRV1 - #55
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DRV0 and DRV1 are bits 5 and 6 of status register 3, as the Registers view has them. Neither constant is used, the binary does not change.
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PR Summary by QodoCorrect SPI NOR SR3 drive-strength bit masks
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DRV0 and DRV1 are bits 5 and 6 of status register 3 (
0x20,0x40), as the Registers view of the web mode and the Android app has them; the constants said0x08and0x10.Neither constant is used: the native build has the same SHA-256 before and after, so this is
no-release, with no new version. Build and tests pass in the container.