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SigmaStar ISP: the flash of a board through the I2C of its SoC - #48
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-m sigmastar sends the SPI commands of the flash drivers through the ISP bridge of a SigmaStar SoC (I2C 0x49: 0x10 + bytes out, 0x11 then a read in, 0x12 the end of the command), after the debug port 0x59 lets the UART pins be the bridge and MSTAR starts it. The I2C master is the programmer's: the CH341A and the CH347 get I2C transactions (stream commands 0xAA; the CH347F switches its pins first). -S is the I2C clock in this mode, -q lists the addresses that answer. NOR, NAND and every operation work as with a chip in the socket; not in the web mode or the app. Tests: ispsim (the bridge with a SPI NOR behind it: READ ID, a read and a page program in I2C parts, the debug port unlock), and the options in the stub tests. Not checked on hardware yet.
As in the SigmaStar unbrick steps of the OpenIPC wiki (-i -q): -q lists the I2C addresses that answer and then the operation runs; -q alone lists them only.
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-m sigmastarreaches the SPI flash of a SigmaStar (MStar) board on its SoC, without desoldering, through the ISP bridge of the SoC over I2C: the way to bring back a board with a broken loader (OpenIPC wiki: SigmaStar unbrick).0x10+ bytes go out on the SPI bus,0x11makes the next I2C read clock bytes in,0x12ends the SPI command (CS high). Before that the debug port of the SoC (0x59) is told to give the UART pins to the bridge, andMSTARstarts it.sendandcsgo to the bridge (src/sigmastar.c), so SPI NOR, SPI NAND and every operation (-i,-r,-w,-e,-v,-a,-l) work as with a chip in the socket.-Por by itself: the CH341A and the CH347 (CH347T in mode 1; the CH347F switches its pins to I2C first) get I2C transactions, the 0xAA stream commands. The EZP has no I2C and is refused.-Sis the I2C clock in this mode: 20K, 100K (default), 400K, 750K.-qlists the I2C addresses that answer, alone or before the operation (-m sigmastar -i -q, as in the wiki steps).-Wrefuses-mand-q).Tests:
ispsimrunssrc/sigmastar.cagainst a fake I2C master with the bridge and a SPI NOR behind it: READ ID through the bridge, a 200-byte read and a 260-byte page program in I2C parts under one CS, the debug port unlock; the stub tests cover the options.Draft: not checked on hardware yet. A SigmaStar board with its power on vectis will be connected for it.