A deterministic real-time kernel at the center of a complete embedded software platform, scaling from 8-bit microcontrollers with 2 KB of RAM to isolated, multicore 32-bit systems with one kernel source, one set of semantics, and one tool pipeline.
Current phase: M1 kernel execution implemented, M2 incomplete; Cortex-M and RISC-V are the first embedded targets (ADR-038). The kernel runs on the native port, on Cortex-M3 and Cortex-M4F, on RV32IMAC, and on the ATmega328P, with embedded conformance configured under QEMU and unsupported cases reported as skips; see docs/architecture/07-roadmap.md for the exact status. The architecture (docs/architecture/), fifteen accepted specifications (docs/specs/), numbered requirements with verification methods (docs/requirements/), three research records comparing eleven other kernels (docs/research/), and an executable reference model that explores the kernel's protocols exhaustively (tools/model/) fix the semantics before the first source file, so the implementation never has to be rebuilt around them.
Start with docs/STATUS.md for implementation and evidence, then docs/README.md for the design. The first supported release targets one Cortex-M controller with native development; isolation, budgets and the broader platform retain separate later gates (ADR-039).
The following describes the target platform. The implemented subset and unverified guarantees are listed in docs/STATUS.md; acceptance of a specification does not imply a shipped feature.
- Isolation-ready by construction. Capabilities and partitions exist at every scale: a pointer on a 2 KB device, hardware-enforced isolation with restartable partitions on an MPU device, same application source.
- Temporal protection. Fixed-priority scheduling with execution budgets and deadline monitoring, instead of silent starvation or priority aging.
- Hardware as data. SoCs and boards are validated descriptions; device tables, memory maps, pin and clock configuration, and linker fragments are generated.
- Observability by default. Deferred-format logging, Common Trace Format tracing, retained crash records, and a versioned debug descriptor any debugger can read.
- Evidence over claims. An executable reference model is the scheduler's oracle; every requirement maps to a test; every timing number ships with its configuration.
- Secure lifecycle. Signed, measured, updatable images; reproducible builds; software bill of materials; disclosure policy; long-term support windows.
- Toolchain independent. EmbCC first-class; GCC and Clang required.
Native simulation and AVR (ATmega328P) first, then Cortex-M (Armv6-M to Armv8-M with MPU and TrustZone), then RISC-V with PMP, then symmetric and asymmetric multicore.
Apache-2.0 (see LICENSE and NOTICE). Contributions are welcome under the Developer Certificate of Origin; see CONTRIBUTING.md. Security reports: see SECURITY.md.
Development process: required checks and branch rules, ordered M2 work, release checklist, and changelog. The current version is development; there is no supported release yet.
EmbLinkRTOS integrates with EmbCC, EmbBuild, EmbDebug, EmbFlash, and EmbStudio while remaining fully usable with third-party compilers, debuggers, probes, and build systems.
The Sphinx site includes the user guide, current C API, architecture/specifications and a generated design-requirement catalog. See documentation setup for the pinned tools and optional publishing workflow.
python3 -m venv .venv-docs
.venv-docs/bin/python -m pip install -r docs/requirements.txt
python3 tools/docs/bootstrap.py
.venv-docs/bin/python tools/docs/build.pyOpen build/docs/html/index.html. Kernel compilation is not required for the documentation build; extraction is not test-coverage evidence.