From 2f456927594f5a49200ea20ac7e6949f9e0794e7 Mon Sep 17 00:00:00 2001 From: Compot Developer Date: Wed, 4 Nov 2026 11:13:39 +0000 Subject: [PATCH] SPI NOR: the bits of SR3_DRV0 and SR3_DRV1 DRV0 and DRV1 are bits 5 and 6 of status register 3, as the Registers view has them. Neither constant is used, the binary does not change. --- src/spi_nor_flash.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/spi_nor_flash.c b/src/spi_nor_flash.c index c650a53..a23f5c8 100644 --- a/src/spi_nor_flash.c +++ b/src/spi_nor_flash.c @@ -94,8 +94,8 @@ #define SR2_SUS 0x80 #define SR3_WPS 4 -#define SR3_DRV0 8 -#define SR3_DRV1 0x10 +#define SR3_DRV0 0x20 +#define SR3_DRV1 0x40 #define SR3_HOLD 0x80 #define snor_dbg(args...)